[XPU] Gate FlashAttention-in-graph on oneAPI 2026.0+ runtime support - #50038
[XPU] Gate FlashAttention-in-graph on oneAPI 2026.0+ runtime support#50038krisclarkdev wants to merge 21 commits into
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FlashAttention SYCL kernels use sycl_ext_oneapi_work_group_scratch_memory, which SYCL Graph cannot capture before oneAPI 2026.0 (intel/torch-xpu-ops#3142): full-graph capture raises "work_group_scratch_memory ... not yet available for use with the SYCL Graph extension". Today XPU users must know to avoid FLASH_ATTN with full cudagraph modes entirely. Add supports_xpu_fa_in_graph() (torch.version.xpu >= 20260000) and gate full graph modes on it in XPUPlatform: - VLLM_XPU_GRAPH_FORCE_PIECEWISE (default on): clamp full modes to PIECEWISE so FlashAttention stays outside the captured graph - safe default, preserves current behavior. - With the clamp opted out on a capable runtime, keep the requested full mode and log that FlashAttention-in-graph is enabled. - With the clamp opted out on an incapable runtime, fail closed back to PIECEWISE instead of crashing at model warmup. Validated on Intel Arc Pro B70 (torch 2.13.0+xpu, oneAPI 2026.0): dense Qwen2.5 and MXFP4 MoE + hybrid GDN 35B decode ~5-6x eager with byte-identical greedy outputs; FULL auto-resolves to FULL_AND_PIECEWISE for UNIFORM_BATCH hybrid backends. Co-authored-by: Cursor Agent <agent@cursor.com> Signed-off-by: Kristopher Clark <krisclarkdev@krisbox.org>
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Required companion PRs for production FA-in-graph (this PR is gating-only):
Please treat those as blockers for claiming the full validated graphs stack; merge order can be flexible as long as they land / pin together. Description updated with the same table. |
Mark torch/image vllm-project#48677, softcap/MXFP8 vllm-project#49813, and kernels vllm-project#485–vllm-project#489 as merge/pin dependencies of the gating-only graphs PR. Co-authored-by: Composer Co-authored-by: Cursor <cursoragent@cursor.com>
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vllm xpu upgrade to oneapi 2026.0 and we don't want to provide backward compatibility. so I think this PR is not necessary. we have another PR update log of this part. #50236 |
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This pull request has merge conflicts that must be resolved before it can be |
Co-authored-by: Cursor <cursoragent@cursor.com>
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This pull request has merge conflicts that must be resolved before it can be |
[XPU] Gate FlashAttention-in-graph on oneAPI 2026.0+ runtime support
Purpose
FlashAttention SYCL kernels use
sycl_ext_oneapi_work_group_scratch_memory,which SYCL Graph cannot capture before oneAPI 2026.0
(intel/torch-xpu-ops#3142).
On older runtimes, enabling XPU graphs with
FLASH_ATTNand a full cudagraphmode crashes at warmup with:
and the practical guidance has been "FLASH_ATTN supports PIECEWISE only".
This PR makes full-graph FlashAttention capture available where the runtime
supports it, and safe everywhere else:
supports_xpu_fa_in_graph():torch.version.xpu >= 20260000.VLLM_XPU_GRAPH_FORCE_PIECEWISE(default on): clamps full graph modesto
PIECEWISE, preserving today's behavior.FORCE_PIECEWISE=0) on a capable runtime keeps the requestedFULL/FULL_AND_PIECEWISEmode and logsFlashAttention-in-graph enabled.PIECEWISEwith a warninginstead of crashing at warmup (fail closed).
Required dependencies (do not merge this alone for production FA-in-graph)
This PR is gating only. The validated Arc Pro B70 / Ornith FA-in-graph
stack also requires the following companion PRs (please land / pin together
or treat as blockers for claiming full graphs support):
torch.version.xpu >= 20260000sosupports_xpu_fa_in_graph()is true and SYCL Graph can capture FA scratch.Context (not merge blockers for this gate PR):
intel/torch-xpu-ops#3142,
vllm#48946 (PVC MXFP4 MoE
graph notes; Arc datapoint below).
is_paddingWA cycle is already handled by kernels#481 + Intel WAs
in vLLM — do not re-open here.
Why this is not duplicating an existing PR
Duplicate-work checks (
gh pr list/ issue search onvllm-project/vllmandvllm-xpu-kernels) found no open PR that addssupports_xpu_fa_in_graph,the fail-closed FULL-mode clamp, or
VLLM_XPU_GRAPH_FORCE_PIECEWISE. Thedependencies listed above are already open; this PR intentionally does not
re-bundle them.
Test Plan
pytest tests/utils_/test_torch_utils.py -k supports_xpu_fa_in_graph(6 cases; no GPU required; pass in oneAPI 2026 container).
(
torch.version.xpu=20260000), oneAPI 2026.0 — eager vs FA-in-graph FULL.device/runtime — eager vs PIECEWISE vs FA-in-graph FULL
(auto →
FULL_AND_PIECEWISEfor UNIFORM_BATCH backends). Correctnesssmokes S1–S7 vs eager.
feature image (same serve profile).
Test Result
Unit tests
No
work_group_scratch_memory/ SYCL Graph error in any serve arm. Onincapable runtimes the fail-closed path clamps to PIECEWISE as intended.
Correctness smokes — dense (Qwen2.5-0.5B-Instruct)
2+2→4)!{4,}loops / emptyFlashAttention-in-graph enabledFULL→FULL_AND_PIECEWISE(FA2 UNIFORM_BATCH)Correctness smokes — Ornith-1.0-35B-MXFP4 (S1–S7)
Arms: A eager, B PIECEWISE, C FA-in-graph FULL →
FULL_AND_PIECEWISE.FlashAttention-in-graph enabled; GDN stays outside FULL capture via UNIFORM_BATCH downgrade.2+2)"4"on every armMAGNETIC-YELLOW-42/Dr. Elena Vasquezbyte-identical across A/B/COutput agreement vs eager (byte-identical / similarity):
Single-stream perf (canary, greedy)
Dense — 8×128-token streamed completions after warmup:
Ornith hybrid MoE — single stream, 8×128-token greedy:
Serving sweep — concurrency × length (graphs ON vs OFF)
Hardware: Intel Arc Pro B70. Model: Ornith-1.0-35B-MXFP4. Profile:
max-model-len=131072,max-num-seqs=2,gpu-memory-utilization=0.9,kv-cache-dtype=fp8, bf16. Grid:C ∈ {1,2,4,8}×(in,out) ∈ {(128,128),(2048,256),(8192,256)}(table shows C=1 and C=8).Graphs ON (
VLLM_XPU_ENABLE_XPU_GRAPH=1,FORCE_PIECEWISE=0,FLASH_ATTN,-cc.cudagraph_mode=FULL):Graphs OFF (same image;
VLLM_XPU_ENABLE_XPU_GRAPH=0,--enforce-eager):Deltas (graphs ON vs OFF) — same image/runtime:
Telemetry over sweep wall (xe hwmon energy counters):
Scope / non-goals
FORCE_PIECEWISE=1). FA-in-graph is opt-in.[XPU] Prefer MXFP8 MoE XPU backend; forward softcap/ALIBI #49813 and vllm-xpu-kernels Flash Attention V2 #485–fix max seq len #489.
re-run here.
AI assistance
AI assistance was used to develop and validate this change. Every changed
line has been reviewed by the human submitter.